Electronic systems including but not limited to data processing systems, often use buses including a plurality of signal lines, to interconnect integrated circuit devices, so that the integrated circuit devices can communicate with one another. Output drivers are generally included in the integrated circuits in order to drive signals that are internally generated in the integrated circuit onto the bus. These output drivers are generally driven by voltage level signals.
Recently, however, in order to achieve high speed operations and/or other advantages, integrated circuit devices that include current mode output drivers have been provided. The use of current mode output drivers can reduce the peak switching current and signal reflections on the bus, to thereby allow low power, high performance communications between integrated circuits.
One technology that uses current mode output drivers is the Rambus technology that is marketed by Rambus, Inc., Mountain View, Calif. The Rambus technology is described in U.S. Pat. No. 5,473,575 to Farmwald et al., U.S. Pat. No. 5,578,940 to Dillon et al., U.S. Pat. No. 5,606,717 to Farmwald et al. and U.S. Pat. No. 5,663,661 to Dillon et al. A device embodying the Rambus technology is also referred to as a "packet type integrated circuit device", because each integrated circuit receives data and addresses in packet units. Accordingly, integrated circuit devices that include current mode output drivers will also be referred to herein as "packet type integrated circuit devices".
FIG. 1 is a schematic diagram of a plurality of integrated circuit devices that are commonly attached to a bus, including a plurality of signal lines, wherein each integrated circuit includes current mode output drivers. More particularly, as shown in FIG. 1, the integrated circuit devices are a plurality of packet type memory devices 101-108 that are all connected to a bus, also referred to as a "channel", that includes a plurality of signal lines B1-Bn. A memory controller 109 also controls the memory devices 101-108 through the bus.
In integrated circuit devices that include current mode output drivers, initialization of the integrated circuit devices upon power-up may consume an excessive amount of time. In particular, in current mode drivers, the current can often vary from driver to driver. Variations may also take place over time. Temperature variations, process variations and/or power supply variations may cause these variations. These current variations may, in turn, lead to voltage level variations on the bus that can result in loss of data and/or other errors.
Accordingly, upon power-up of a system including integrated circuit devices with current mode output drivers, it is generally desirable to set the output current for each of the output drivers in each of the integrated circuits. This current setting is generally performed as part of initialization. More specifically, for each output driver, the current setting operation can set the number of pull-down transistors to be turned on in the output driver in order to set a characteristic impedance and a target output low voltage (VOL) of the integrated circuit device.
A system for setting current in current mode output drivers of integrated circuits is described in U.S. Pat. No. 5,254,883 to Horowitz et al., entitled "Electrical Current Source Circuitry for a Bus", the disclosure of which is hereby incorporated herein by reference. FIG. 2 is a schematic diagram illustrating a conventional current control system, as described in the above-cited U.S. Pat. No. 5,254,883. For ease of explanation, in FIG. 2 only circuits related to the current control for output drivers are shown.
Referring to FIG. 2, a conventional packet type integrated circuit device includes a request packet analyzer 201, a register read and current control enable circuit 203, a logic circuit 205, an output driver 207, a current control circuit 209, a reference pad 211 and an output pad 213.
For the current control of the output driver 207 connected to the output pad 213, a request packet RP is input to the request packet analyzer 201, and the request packet analyzer 201 analyzes the request packet RP. The register read and current control enable circuit 203 generates a current control enable signal CCE and a control signal RR in response to the output of the request packet analyzer 201.
The logic circuit 205 receives the control signal RR and current control bits ICTR0 through ICTR5, generated by the current control circuit 209, to generate control signals Q0 through Q5 that control the current driving capability of the output driver 207. The target VOL (output low voltage), which represents the current driving capability of the output driver 207, is determined in response to the control signals Q0 through Q5, and the output diver 207 drives the output pad 213 to set the target VOL. The current control circuit 209 receives the voltage VOL1 of the pad 213 and a voltage Vt applied to the reference pad 211, to generate the current control bits ICTR0 through ICTR5 in response to the current control enable signal CCE. Further details of operation of the system of FIG. 2 may be found in the above-cited U.S. Pat. No. 5,254,883.
Unfortunately, initializing all of the output drivers in all of the integrated circuit devices that are attached to the bus may consume excessive time. For example, if there are N output pads in each integrated circuit device, then current setting is generally performed N times for each integrated circuit device. If there are eight integrated circuit memory devices attached to a bus, 8N time periods of current controlling may be needed. This time may be excessive for high performance systems.